1. Technical Field
The present invention relates to a testing apparatus. More specifically, the present invention relates to a testing apparatus that can simultaneously test a plurality of wafers under test.
2. Related Art
Integrated circuits are produced by performing various steps such as forming a large number of devices on a single semiconductor wafer, glass wafer or the like, then dicing the wafer into dies, and finally packaging the dies individually. Alternatively in the fabricating process of ball grid array (BGA) devices, the individual dies are packaged before the wafer is diced.
In both of the manufacturing methods mentioned above, the circuits formed on the wafer may be tested prior to the packaging step. The test in the pre-packaging step involves pressing probe pins against target locations on the wafer under test so that the circuits of the wafer under test are electrically connected to the circuits of the testing apparatus. The testing apparatus then transmits a test signal and the circuits of the wafer under test process the test signal. In this manner, the testing apparatus can evaluate the functionality and performance of the circuits.
Japanese Patent Application Publication No. 08-306750 discloses a semiconductor testing apparatus having a changeable probe card that generates a test signal, in which a self-diagnosis board that examines the operation of the semiconductor testing apparatus is mounted in place of the probe card. Such a semiconductor testing apparatus enables a variety of tests to be performed by switching probe cards and can easily examines itself by having a self-diagnosis board mounted thereon.
Japanese Patent Application Publication No. 2000-346875 discloses a probe card that supports a needle serving as a contact point with a wafer under test, in which the probe card has a heat generating pattern to comply with deformation of the wafer under test, thereby achieving an excellent contact with the wafer under test. Furthermore, Japanese Patent Application Publication No. 2001-077160 discloses a technique of improving the quality of a test signal by providing a contact point connected to a ground on the same surface as a needle functioning as a probe pin.
In recent years, the scale and functionality of integrated circuits have rapidly expanded. Thus, necessary tests have become complicated and an increasing number of types of tests are required. This tends to increase the time required to complete the tests of each integrated circuit.
Furthermore, the production quantity of integrated circuits have significantly increased due to the widespread use of diverse electronic devices. Therefore, the time occupied by the test step during the overall manufacturing process may affect the manufacturing cost.
In addition, since the time required to complete tests has increased, the equipment of the testing apparatus such as a handler to transport wafers under test has a lowered operating rate. This lowers the utilization efficiency of the testing apparatus and then contributes to a relative increase of the test cost.
In light of the above, it is desired to raise the throughput of the test step in the integrated circuit manufacturing process. Another demand is to improve the utilization efficiency of the respective constituents of the testing apparatus.